Digital differential analyzer



July 1, 1958 I F. G. STEELE ETAL Y 2,841,328

DIGITAL DIFFERENTIAL ANALYZER 9 Sheets-Sheet 1 Filed March e, 195o July l, 1958 F. G. STEELEV ETAL 2,841,328

DIGITAL DIFFERENTIAL ANALYZER Filed March e, 195o 9 sheets-sheet 2 July 1 1958 F. G. STEELE ETAL 2,841,328

DIGITAL DIFFERENTIAL ANALYZER Filed march e, 195o 9 sheets-sheet 5 July 1,1958 F. G. STEELE ET A1. 2,841,328v

' DIGITAL DIFFERENTIAL ANALYZER Filed March 6, 1950 9 Sheets-Sheet 4 rro. Mey

July 1, 1958 F. G. STEELE ETAL 2,841,328

v DIGITAL DIFFERENTIAL ANALYZER Fi1ed Maroh 6, 1950 9 Sheets-Sheet 5 Irfan/vtr 9 Sheets-Sheet 6 F. G. STEELE ET AL DIGITAL DIFFERENTIAL ANALYZER Irfan. #fr

July 1, 1958 Filed MaICh 6, 1950 F. G. STEELE ET AL 2,841,328.

DIGITAL DIFFERENTIAL ANALYZER 9 sheets-sheet 7 5 faq- Hap 55 ro CoM/2 fun-H0753 (ma r Ero f//v y afp-Ha# f/J" man conm zur: :1:1

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July 1, 1958 Filed March 5, 195o 6 1111.151 8 ,2 r m l .\l .l x. Q M 52! J a m T. yd W E m. W m o/o F July 1, Y1958 FQG. STEELE ETAL 2,841,328

DIGTAL DIFFERENTIAL ANALYZER Filed March 6, 1950 9 Sheecs--SheecI 8 IrraAA/r July 1, 1958 F. G. STEELE ETAL DIGITAL DIFFERENTIAL ANALYZER Filed March 6, 1950 9 Sheets-Sheet 9 www United States Patent() DIGITAL DIFFERENTIAL ANALYZER Floyd G. Steele, Manhattan Beach, and Richard E. Sprague and Bernard T. Wilson, Los Angeles, Calif., assignors to Northrop Aircraft, Inc., Hawthorne, Calif., a corporation of California Application March 6, 1950, Serial No. 147,862 73 Claims. (Cl. 23S-61) This invention relates to computers and more particularly to a novel means and method of performing the process of differential analysis. n

In differential analysis devices it is desired to generate solutions to dierential equations, i. e., equations whose variables are related and expressed in the form of derivatives and differentials.

In general, two generic classes of computers have heretofore bene known. One of these is the analogue computer, sometimes referred to as the continuous variable type computer, which is best known and demonstrated in its mechanical embodiment as the Kelvin wheel-and-disc integrator. The other of these classes is the digital computer. This latter class is further characterized by the fact that it employs, for example, electrical signals for representing numerical digits.

' The present invention is primarily concerned With a novel means and method of performing the process of differential analysis which may be considered broadly as a hybrid of these two previous types. Y

On examining these devices for performing integration it becomes readily apparent that the character of approach of the analogue computer, for example the wheel-aud-disc type integrator, is more direct and much simpler than that of the digital computer. This is because the wheel-and-disc integrator operates directly upon a differential equation as it is ordinarily written. It operates by methods of the calculus.

The digital computers, on the oher hand, require that a differential equation can be transformed into a numeri cal form before it can be solved. An elaborate memory system is needed for storing subroutine numbers and orders. The preparation for setting up the equation in the computer is generally quite difficult and lengthy.

Thus it is seen that of the two classes of computers, it is the logic of the analogue computer that is most clearly a part to that body of mathematics, calculus, which it seeks to augment.

The digital computers, howeverhave many advan tageous features. After once getting a problem coded for a digital computer, the problem can be solved on it in a very short time, much shorter than on the analogue computers. This is due to the fact that digital computers embody the advantages of extremely fast acting electronic operations. Furthermore, the digital computers are inherently more accurate than the analogue computer. By representing magnitudes of variables by pulses, rather than proportional voltages, rotationsof shafts, etc., the digital computers have the abstract property of working with numbers and thus the computations on them can proceed with al1 the rigorous accuracy associated with numbers.

Thus it is made evident that it would be highly desirable to have an integrating device which could embody the simplified, direct logical approach to a diierential equation employed in the analogue computers while also gaining the advantage of speed and accuracy associated with the digital computers.

In order for a differential analyzer to have these desirable features, it has been determined that a single fundamental integrating unit must satisfy certain requirements which, although they are all inherent in a mechanical manner in the wheel-and-disc type, must also be incorporated in an electronic digital manner in the proposed device. These requirements for an integrating device are as follows:

(a) It must receive two independent inputs of varying magnitude and produce from themV one output of varying magnitude.

(b) If the time rates of change of the input magnitudes are called and the time rate of change of the output magnitude must be where the relation of the variables is such that dz da: n-Kyn K being a lconstant which may be associated withrthe integrator. K

(c) Both of the inputs, and the single output must all be of like nature, just as the wheel-and-disc ltype represents magnitudes by shaft rotation, the present integrator must represent magnitudes by sums of'electronic Y pulses;

(d) To simulate mathematical processes, the magnitudes involved must be capable of assuming values defined as positive or negative in sign.

lt is therefore the object of this invention to provide an integrating device having the requirements above Vset forth as being'desirable and others which will be made clear in the following specification.

Briefly, the present invention comprises aV counter for storing a number whose magnitude is being varied by ,a rst pulse train feeding into the counter. A transfer above action is used to generate a third pulse trainsuch that the time frate Yof pulses of the third train with respect time rate of pulses on accordance with the magnitude "of thenurnber trans-Y Vpreferred embodiment of the the proce'ss'ofintegration.: j

Y Figure'9 is agraph'of the 'dependent variable y illu'sconnections of associated circuits.

the second train is varied in ferred from the counter.

Associated with the above, circuits are provided for enabling the effective number in the counter to increase Vor decrease Vin accordance with positive and negative polarity pulses of the first train, the polarity of the pulses being usedV to indicate the sign. The sign arrived at by the number in the counter is then sensed along with theY sign or polarity of the pulses on the second train and is thus used to determine"`th e sign or polarity of the plsesn the third-train!V i The-present invention is a typical exampl'elof mathematical machines that are widely used because "they can perform'fcertain Ycalculations lmoreswiftly than1any human calculator could by use ofbrain andhand. MathematinilV machinesV can bedefined' as mechanisms which Vprovide'- information Vconcerning the Vrelationships between "a specified set of mechanical'concepts. But itis to'belept in mind that mathematical machines" suchY l Y"as described herein can only Apractice'inethods which are capable of being performed by'hand, provided Vonly 4 Figure 18 is a graph showing the values of the sine and Vvcosine functions as readin the'Y counters of the integrators in Figure 17.

Figure 19 is a graph illustrating the operation of certain components shown in Figures 4, 5 and 6.V

Referring first to Figure l, the'well-known mechanicalV wheel-and-dsc type analogue integrator is illustratedas an aid in explaining the theory of operation of the present invention. There a vertical wheel 10 hasv attached at its center one end of a horizontal shaftill.

Horizontal shaft 11 is cantilevered from a fixed bearingV pedestal 12 in which it is rotatablymounted` jItV should be noted that the shaft 11 is carefully restrained from" 'Y 'moving axially with respect to theV pedestal 12. The

periphery of vertical wheel10, whoseplane is thus fixed,

' rests on a horizontal disc 13 which can Vbe rotated about 1 Vthe axis of avertic'al shaft 14 extendingdownwardly 'that'suflcienttime and'manpower are available.. Y'It is mainly for conservation of time and manpower that Y the methods' involved are incorporated in vspecific appara'tusithat is abstractedlyequivalent to a .laborious and and'time consuming original system.

' This invention' will be more'fullyunderstoodrby reference to the following description ofthe'appende'd draw- `ings,"in"whi`ch: f Figure l is ,an illustration Vfor V depititiugthe theory of operation 'of the wheel-and-dise 'type integrator.V

Figure V2 isra schematicdiagram` for depicting the'V theory Vofjoperation of the digital counterpart ofthe integrator inrFigure'l. Y

Figure 3 is a graph illustrating, generallyQhoW the`V present invention performs the processof integration.

Figure 4 is a modified embodiment of the digital integrator operatingin the serial, additive-transfer manner.

, Figure 5 is the preferred 'arrangement of the modified embodimentzin Figure 4.

Figure r{Sfis a"schematic'villustration ofthe` complete from its center. VVertical shaft 14, in turn, is rotatably supportedv in va movable carriage 15 which is connected so that it can be driven along horizontal guide rails 16 by the rotation of allead screw 17.` This vaction enables the distance of the point yofcontactof the wheel 10011 the disc 13, from the center C of the disc 13, to be' varied; since the carriage 15 canrbe moved horizontally with'respect to bearing pedestal, 12 while the wheel-10` is'always atffa fixed distance with-respecttdthefbearing pedestal 12. Y Consider the point of-contact of wheel 10. and d isc 13 to be,` at a given-instant, a distance y from the center VC of disc 13. Ifthe disc 13 rotates through 'aafsmall fraction of a turn, say dx, due -to a rotationV` on vthe vertical shaft14, the wheel 10 willrotate through ydx/a z ontal shaft 11.Y In

digital integrating circut'includingY the circuits'for enablingthevariables to assume values defined as positive or negative in sign.

' Figure. 7 isa wiring. diagram, partly fragmentary, of

i a typical stage'of the X counter' and Y counter; "and a' Y gate.

Figure 8 isY a graph illustrating as example of how the trating the, operation ofV the 'sign. cha'nging; circuits. "Figure-10 Yis a "diagram ofthe ,neon returnV `circuit .-Figure112 is a schematic wiring diagramV of the Vcomplementip-op circuit;and. tl1e normal and complementV '.g'ates; and shows in V,particular `the .interna1:poin ts of Figure 1 3 is a schematic wiring diagramofthe sign-y plement pulse former and the'zero puls e fo1 mer7circui ts.

foutput'pulse'for'mer and sign changer circuit.

5o digital integrator performs Ywhich enables a' continual visualV indication to bernade ofv the actualy number in the Ycounter. Figure 11 is 4a diagram, partlyschematic, slrllvvingtheV ,'-dzwpulse"complementing circuit. 'l Y- turns. Thisrortation-of'the-wheel 10is evidenced-as an 'equivalent small fractiongof a-turn, say dz',V on -thehorithe above` expression, a` is the radius lof the wheel 11).

1 lfthedistancey is now .varied byajsmallfraction of r :LturrL saydy, on the lead'sicrelw 17"whileQthe disc 13 is rotating, the total rotation of the v-wheel 10 and couse-V quently the horizontal'shaft 11 isfthe sum of each of 'the contributions ydx/mithatis, f `ya'x/av turns. It is-to to be noted ,hereY that 1'/ a ,ca'nfbe taken outside ofthe integral sign, since it is .a 'constant,'and maybe "desig Ynatevd 'generally asY the constant K.

This-completes thedescriptionof-the analogue integratorV which enables one to produce solutions to differential l equations mechanically andwhich hasfbeenY presented herein 'to intro du c:e` the logicof the digital Vintegrator of 'Y the present invention.

The Vproportionality characteristic lcommon to allV analogue devices eXists inthe wheel-and-disc'.integrator between Vshaft rotations and Vthe variables ofi Vthe differential equation. Each variablelin thewequationis' represented somewhere in the machineby a rotating shaftQY The totalangleof rotation of ashaft-fr'om some; reference positiongis proportionalV toV the magnitude of the variabler', The sign of` the variable, is denoted by clock- VWise or .counter-clockwiserotation"from .the reference the direction the shaft isrotatingdetermines theV s ign of Y The independent Yvariable shaft -for one'V integrator, whichY in -this :case is vertical-shaft V14,l `cor-` 'f responds tothe variable x-and'is`-generally Adriven by-a motor; f andV the'vrati'o of the lspeed -ofrotationf of any f digita'l` integrating circuits of the present invention 'arle'V Y usedfor'generatig the A sine and "cosine" functions. 75

position. YAThe "rate of rotation ofV thesh'aft Vis proportignal to the time derivative-"offthe'variable,'antl'again,v

the derivative.

other shaft, say Vthe lead s crewi17 (which corresponds to f the Vvariable y)"to the'vertical shaft I4-is alwayspropor- Y Y v This operation may r`be further -understood Vbyfconsider- 'ing derivativesandintegrals separately. `Ifthe-"speed off `rotation fof* the -iindependent variable `shaft 14,-is,V for 4exdened as tix/dt and it rotates'for t seconds., its total rotation would be ample, through the range x1 to x2,

In-other words, the speed of rotation of the shaft is proportionalrtolthe time derivative .I i

of the variable x; and the total rotation (x2-x1) of the shaft is proportional to the integral of dx.

In the mechanical integrator, as described, the lead screw 17 is connected in such a manner as to vary, at a rate, the position of the contact point of the wheel 'with respect to the center C of the disc 13. The disc 13 is rotated by the independent variable shaft 14 at a speed speed Regarded in this sense, the integrator is a multiplier. Sincethe output speed as above shown; the total output rotation 1 I1 Y v z=f de (L z2 y vBecause of these facts the speeds of each ofthe shafts may be rightly dened as being proportional to the time derivative, or rate of change, of the variable it represents. It is also proper and proves to be advantageous in understanding the present inventionto treat the speeds of the shafts as being proportional to the differentials of the Variables, sincethe time term, though always implicit, cancels out.

Referring to Figure 2, the basic digital integrating circuit of the present invention is schematically illustrated there and will now be generally described. This circuit is composed, in general, of three elements: a rst counter functioning as an integrand storage 18` and having an input lead 19; a secondV counter functioning as a remainder accumulator 20 and having an output lead 21; and, a transfer device 22 which has a `second input lead 23. Transfer device 22 serves the function lof transferring the existing number y from the integrand' storage 18 into the remainder accumulator 20 each time a pulse input is received on second input lead 23.

4Each electrical pulse, designated dy, received on the input lead 19 to the integrand storage 18, represents a small unit increase of theintegrand y and causes the integrand storage 18 contentV to increase by one. The nature of the transfer device 22 is such that as each input pulse, representing the variable of integration dx, is received on second input' lead 23; rthe number y existing asiatica Its output lead 21 then emits an output pulse dz, and

in the integrand storage 18 is transferred in an additive manner to the number in theV remainder accumulator 20 While being retained in the storage 18.

The remainder accumulator 20 has a given capacity, in this case of the same capacity as the integrand storage 18. As the existing y number is continuously added into the remainder accumulator 20, as dictated by the dx inputs, the Iaccumulator 20 soon reaches its capacity.

`accumulator 20 starts to count from zero again. It is to be noted that in forming the dilerential combination of the dependent quantity y with a variation in theindependent quantity dx (as Vshown in Figure 2) the value of the dependent quantity y registered in the storage 18 is registered in the accumulator 20 in full signicance when dx has a value of one. That is, the registration of the value held in the storage 18 by the accumulator 20'is unlike the accumulation or registration of partial products which occurs in a conventional multiplication. This is so because there is no prearranged orderly shifting of the signals registered, to thereby alter the significance attached to the quantity y as it is repeatedly registered in the accumulator 20, as would be the case in the accumulation of partial products.

It is to be noted that the integrand lstorage 18 does not provide for an overow output, its capacity limits the maximum value of y which can be transferred in the remainder accumulator 20.

The nature of the transfer device 22 can take any one of several possible forms, in transferring the y number out of the integrand storage, such as series, parallel, or staggcr additive transfer. In the embodiment of the present invention which is to be described -in detail in the ensuing discussion, a series additive transfer is utilized.`

The'counters used in the digital integrating circuit for the storage 18 and the accumulator 20 can be either of a decimal, binary or any other radix desired as long as they are both consistent. However, in the embodiment of the invention which is to be described in detail, binary counters are used since they present certain advantages when used with other chosen components of the circuit.

The similarity of the digital integrator circuit of the present invention to the previously described wheel-anddisc integrator is now revealed in several aspects.

The basic idea of the present invention, in accordance with the foregoing, is in the representation of a variable by a train of electronic pulses ona conductor instead oi a shaft rotation.

The rate at which thesevelectrical pulses appear on a conductor corresponds to the speed of rotation of a shaft on the wheel-and-disc integrator, i. e., is proportional to the derivative of the variable. The totalv number of pulses on a conductor in any interval is proportional to the change in the magnitude of the variable during the interval.

Further, in the mechanical integrator, the relative position of the wheel 10 on the .disc 13, which corresponds to the variable y, can be thought of as a memory device, i. e., it stores a single number y which is being changed in magnitude in accordance with the rate of rotation of the dependent variable lead screw 17.

as a device which integrates the rate admited to it with respect to time, i. e.,

Since y now varies in magnitude, the previous equation no longer holds. Instead, the integral or the output rate of ones must be expressed as:

Where the diierentials dz and dx are not true diierentials but the discrete changes in the variable as previously described.

The above equation essentially states that the rate at which the accumulator 20 produces ones is proportional to the product of the variable y and the input rate of ones into the transfer Vdevice 22. The last term dr dtN corresponds to the rate of change of the round oi of the increment dz.

Thus it can be seen that the output rate of onesl on the dz output lead 21 is now variable with respect to the input rate of ones on the dx second input lead 23. This variableness in the rates of ones into and out of the machine is directly proportional to the variable number y, within the accuracy of the remainder term drN The concept of the rate at which onesV are entering and leaving the 'integrator circuit, for the case of an input rate d: Y of ones also, will now be further clarified. Since neither of these operations dx dz a and@ dz 'EF and then, these instantaneous time rates at which ones enter the transfer device 22 of the integrator can be deined as equal to dx dt and the instantaneous time rates at which ones carry out of the integrator from the accumulator 20 can be defined as equal to dz d:

The concept of such rates is both useful and correct to the extent that the summation process duplicates the integrating process.

As explained in connection with the mechanical integrator, no substantial error is made in the digital integrator in considering the rate of change of a variable as being proportional to its diierential instead of its derivative, since the time term, though always implicit, cancels out.

Thus, to preserve the similarly of the digital integrator to the mechanical one and to take advantage of the simple logic of the mechanical diterential analyzer, inputs 19 and 23, and output 21 of the digital integrating circuit of Figure 2 have come to be known as the dy and dx inputs and the dz output, respectively. This nomenclature persists throughout the remainder of this discussion and is adhered to both in developing the logic of the fundamental digital integrator circuit and in interconnecting several such integrator circuits to solve complex differential equations.

The numerical device just examined satises the first three requirements as set forth for the integrator in that it combines two input rates into the specied output rate and produces the output in kind. For example, the dz output of the device can be coupled back to form its own dy input to produce an exponential function. It will be noted that a one may serve either as an incremental unit or as an instruction.

Thus, the digital integrators may be considered as a set of devices which communicate between themselves in the monary or unitary number system, and which operate upon the intel-communications by means of numbers internally stored and expressed in any numbering system convenient. Numbers may be looked upon here as the means of establishing the accurately controlling streams of ones. These ones are, in turn, counted to form other numbers.

The stored numbers act fupon a received rate of ones by deleting units from it, and therefore have the nature of variable or fixed rate dividers.

The elect of an integrator is to transmit a unitary rate dz which is equal to or less than the dx input rate, never greater. lf the value of a dependent varia-ble, z, is to be found by counting the dz or output rate, then, for example, between 1104 and l05 units or pulses must be counted in order to express z as a ve place decimal number. lf the rate reduction of the integrator is nominal, this may, ordinarily, 'be accomplished by the admission of no more than dx inputs. lf the rate reduction of the integrator is excessive, the number of dx inputs required to achieve the same accuracy of expression for z must be greater. Since the time required to perform an laddition cycle in the integrator will usually be xed, the accuracy achievable in a limited time and with a limited amount of equipment will therefore depend, among other things, upon the extent of rate reduction in the integrators.

Y Y counter.V

' on". gate output .line

asse-3.28

Returning to Figure 2 and lghqluation La and; dt N dft. dN it evident that the Vrate reduction ratio is essentially established by' the ratio of the variable y to the constant N. Therefore, y must be kept as large aspossib'le consistent with the vsize of the storage `18. The Imaximum valuewhichyV takesV during a computation willtll the storage-'18; Vthat is,will have `a digit represented in the highest stage. At no time, of courseycan Ythe capacity of the storagellS be exceeded. In the 'binary system, if the averagernu-rnerical value ywhich y takes in the storage 1S during computation is half its capacity, then the average rate out is one half of the average dx ratein. If this rate is allowed to cumulate in the storage 1'8 of another'integrator', then that storage will receive enough kunits'to iill half of Yits capacity. Since itA will have an5initial`setting,however, which will occupy on theaverage half of its capacity, the storage will be Elilled.

gonsi-derthe vbinary Yiiuinlier y appearing in the .Y Y counter 28. iIf y is regarded as anv integenthentheY Y counter may contain any integer from 0, 1,2'etc. to 2"-11. Y

`When y=0, all the Y stagese'are zero, all Y gates are closed and the output'pulsesy dz Von gate output line 30 equalsV Y e Y jodx Y j When y= 1, the extreme right lhand Y counter stage is Y j in its one condition, the'Y gatey 27 at that point isopen e' and When y=2, the (.rt- )thstage from the left'is one,

arid Ythe .rat through itslYfgate makes .Y Y

dz,` 2da: da:

. When )1 -254. 1, all tlieY counter*stages*areY one, all

shown'in'Figure 2, the additivetransfer of the y number Y in the storage 18 can'be accomplished by series,'pa`rallel',

or stagger methods. fv present embodiment of the invention'accomplishes this'aidditive transfer in a series manner' as willfjnow ybe described. 1 Y Y Y 'Referring toVV Figure 4, `theblock diagrarngof the series additive transfer'circuit'is' illustrated. "In effect, this ,cir-AV cuit niultipliesa pulse Arate fed in on VtheY dx input line '-by a'nurnberV y Vheld in a1Y binary counter `28. This is`ac complished yby' lfeeding dx pulses into Yan X binary counter,V

2 4. AOutput line'sfZS'areztken'froineach ofthe'rstages in Vthe X counter 254. V""iac'h` of? these output linesj25 'is Y connected toV oneo'f Vtliefgate's 27,''f a bank of Y gates.' Y

Y'counter 28, which Lhasthesa'tne number of fbinary stages as the'X counter24 is located below 'the Yi gates e V27.V Each Ystage of the'YcounterrZSQ-has an output stage lead Y29Y which connects to one'of the Ygate's 'andopens Yorclose's this Y gate in acccrdancejwithlthe stateofgthe stagej v |It should be notedV as shown Vin Figure 4 'that the lowest order stage of the X counter 2'4 is jon theleft,"while the lowest order stage lofithe Y' counterAjZS is on the right. Thus Vthe dx pulses are fed into thejleftof the X counter, VWhile Ythe'dy pulses are fed `into the right in theY Thus itcanv'be seen that as the X Vcounter receives'dx pulses, output pulses are taken from each 'of its stages, Vin,accordance.with the binary division of the dxrratefby d the Xstages.

Y rlfh'esevoutput pulses are sentthroughjY gates 2.7, each-of theV Y -gates is controlled bytheV stage Yffthe Y counterV directlyY 1below it. YIn eiect, the .pulses Y pass Ytlriro'ugh these gates if the Y stages are .in theirfone l condition'and do not pass if theyare in theirfzlero condition.

gates 27 are open; and the output rate Vis In Figure 119, a chart is'shown illustrating theoperation of the counters 24.. Sincethe.X.lcounters24 -arecon-' nected in cascade arrangement, the triggering of each j 1 stage is controlled by the `operation of the previous stage,

Before the introduction ofany'pulses, the left tubes n each ofthe stages are cuto'tf.V This is'illustratedbythe letter {f Ijijinfthel-chartgshown in Figure Y19 to indicate that Va relatively high voltage is produced on the 4plate Aofthe left tube in each stage. The left tube ineach.stagecorre Y sponds to the Vtube Y@ in the-sstage shown in Figure 7. Y

Upon the introduction "of, a Yfirst fdx pulse, Vthe` first Y Vstage in the X counter 24 is triggered so Vthat kthe right'tube Y Ybecomes cutoirran`dffthe left 'tube corresponding 'tothe f tube YVT, becomeslconductiye. V`When the-left'tubegjnthe i first stage fbe'comesfconductive, a relativelyilow Vvoltage isV fproduced on the platef'ofvthefftube, asirindicatedrby the f., letter L for the stage. As will Vbe disclosedin detail hereinafter, a signal prasses'i'through the stage Yin'thegYV Y gates 27*V associated with tha-first stagein the counter 24-VV when theV left tube in the associated stage of the Y counterVV 28is conductive at'thestimefthatzthefleft tubeinftherst i stage of the Xrcounter 24 becomes conductive.

Y counterV 24 is introducedj-tio the secondstage YofV the counter to cut Votrthe rightftube .in the second stage, and.

Y to make `the lefttubeinfthegstage conductive. .When the j The `Y gates 27 are connected in parallel to Ya lgate out-A l put liner) 'so that each pulse passinga'Y gatef2-7 Vfed 39 as'jone' of/a Vtrain ofY pulses ",dz.'

" time;

left)Y tube'AV in i the second stageffopf" the X counter `247i ybecomes conductive, a signalrpasses'throughthe associated 'stagepf the Y gates Z'Ijprovided that the lefttube of the- Y Y Vassoclated stagein thegY Vcoiiir1'te'r28 is also, conductive.

A -signalgdoes not pass Vthrough the stagein theQY gatesV 27rra's soci atedvgwithrtheiseconlnstage ingthe X counter 24]@ when-theflefttube. njthevassociatedstageof'the`.Y counter, Y A28 isfnon-,onductive attheltiniethat the left 'tube inthe Y second-V stage@ of; .the r XS. counter V24. becomes conductivel Y Y The,leftgtube'irr'thefrst-stage of. the'X counter 24l again becomes..V conduetiveuponfthe frintrroductri-on oliv aV Vthird izr'x pulseY This causesziawsignalsto pass through Ytheirs't stage 7 Y in the'Ytgates 127 vproviclecb thatftheileft-V tube in. .the asso- 'i 'f ciated/'stage ofthviY-counter28vgisalsocondctive atthis y i However, ansignal doesV not pass eth'rouglimthefY second stagevof the Y'gatesZTupon the introduction Tof theY dx pulse Veven fthughV the left tube in'y the i l second stage of the X counter 24 and the left tube of the associated stage in the Y counter 28 are both simultaneously conductive. The reason for this is that a signal can pass through a stage of the Y gate's 27 only when the left tube of the associated stage in the X counter 24 changes from a condition of non-conductivity to aV condition of conductivity to produce a negative pulse on' the plate of the tube. y

The introduction of the fourth dx pulse to the X counter 24 causes the right tube in the rst stage of the counter to become conductive. The resultant negative pulse of voltage on the plate of the right tube in the first stage triggers the second stage into its alternate state of operation so that the right tube in the second stage becomes conductive. This in turn causes the third stage in the X counter 24 to become triggered so that the right tube in the third stage becomes cut ot and the left tube becomes conductive. When the left tube 'in the third stage becomes conductive,` a signal passes through the associated third stage in the Y gates 27 provided that the left tube of the associated stage in the Y counter 28 is also conductive at this time. If the left tube of the associated stage in the Y counter 28 is not conductive at this time, a signal does not pass through the third stage in the Y gates 27 when the left tube of the third stage in the X counter 24 becomes conductive.

It will be seen from the chart shown in Figure 19 that the stages in the X counter 24 are able to pass a signal through onlyone of the stages in the Y gates 27 upon the introduction of each dx pulse. A signal is able to pass through one -of the stages in the Y gates 27 upon the introduction of each dx pulse provided that the associated stage in the Y counter 28 is in a proper state of operation. Signals are able to pass through each of the stages in the Y gates 27 a weighted number of times dependent upon the relative position of the stage in the gates. For example, the rst stage in the Y gates 27 is able to open substantially twice as often as the secondY stage; the second stage is able to open substantially twice as often as the third stage; the third `stage is able to open substantially twice as often as the fourth stage, etc. The stages are able to open in a particular pattern because of the cascade arrangement yof the different stages in the X counter 24. However, similar results would be obtained if the stages were able to open in a random fashion havinga weighted effect corresponding to that disclosed above.-

When all of the stages in the X counter 24 have been triggered so that the left tube in each stage is conductive, the introduction of the next dx pulse to the counter causes the left tube ineach stage to become cut off. Since none of the stages in the X counter 24 has its left tube passing from a condition of non-conductivity to a condition of conductivity upon the introduction of this dx pulse, none of the stages in the Y gates 27 is able to open even though the left tubes of stages inthe Y counter 28 may be conductive. Thus, when n stages are used in the X counter 24 and Vin the Y gates 27, various stages in the Y gates 27 are 4able to open only during 2-1 times out 'of each;

2n dx pulse.

A slight error may be produced during the one pulse when none of the stages .in theY gates 27 is able to pass a pulse.V Pl`his error is quite small. For example, if l2 stagesV are used in the X counter 24 and in the Y gates 27 an error of approximately approximately 0.02% y Y It isapparent from the vcases mentioned that, in general,

Referring toY Figure 4tl1e output pulses dz' on gatel output line 30, are seen to feed into two parallel dz outputlinesl'and 32. The dz' pulses are fed outdirectly on dz output line'32, but the dz pulses are fed through an R counter 33 before being fed out on the otherl dz output line 31. Forthis case also', it shouldvbe noted that the R counter 33 has the same number of stages as the X counter'24 and the YY counter 28.

It is to be noted vthat in making use of integrators for solving problems that the output from one integrator is fed back into one -of its own inputs or into the inputs of another integrator; the two dz output lines 31 and 32 provide the pulse rates that must be fed into the dy inputs'and the dx inputs, respectively.v l

It should be made clear that since the present embodiment of the integrator is employing the series additive transfer method; the dx pulse rate must be relatively high. For example, in order to transfer once the y Vnumber existing in a Y counter having .n stages, 211V d x pulses must be fed into the integrator.

cannotbe fed into iboth the dx and dy inputs, but that the R counter, functioning as a rate divider, must reduce the rate of dz' pulses /n for feeding in on dy inputs.

Thus it is seen that a digital integrating circuit has been described which uses a serial additive transfer method for transferring the y number into the Y counter, i. e., transfers the y number from the Y counter4 one stage at a time.

Referringv next to Figure 5, a slight modification of' the circuit in Figure 4 is provided. It is shown there that the R counter 33 has been shifted from the dz output line 31 (Figure 4) and placed in the dy nputline" Thus the advantage of this set-up is' Only one dz output pulse line is now to the integrator. made obvious. required. The dz pulse rate is now automatically available as the high rate needed for dx inputs; and this same dz pulse rate can now be used as the dy inputs, the necessary rate division needed for the latter input being now made by the R counter 33 which will henceforth be called the lirst half of the Y counter 40.

By comparing the theory of operation of the general integrating circuit'shown in Figure 2 with the embodiment shown in Figure 5, it isl now apparent that whereas in Figure' 2 the" remainder accumulator` 20 was used for holding the roundot portion of the increment dz, the embodiment in Figure 5 can be thought of as using the R counter for holding the roundoi portion of the increment dye which is the notation given to the carry pulse from the R counter 33 to the Y counter 28. This point of and one particular modification which employs the serial additive transfer method.

Up'to now no mention has been made of the fourth requirement as previously set forth for a digital integrating circuit. ToV meet this fourth requirement, the integrator must be able to attach a Isign to the ones which it produces, that is, it must be able to produce either plus or minus ones. Further, it must be able to utilize signed inputs.

Specifically: Y

(a) The Y counter must be able to contain either positive or negative values of y, hence, an indicator must be provided for the sign of y.

(b) The Y counter must receive a plus one in such a manner as to increase by unity in the least significant place` the value of y if its sign is positive, or decrease it similarly if the sign is negative. The reverse condition must hold if a minus one is received.

(c) The sign Vof the output must be made negative iff the sign of y is neg'ativej and Athe sign of dx is positive.

Y (d) 4The sign of the output, including that eEected by Thus it can be ap-A preciated that the dz pulses appearing on gate output line condition (c) must be reversed if thesign of a f one Inccrnpar'nvgl the. problemfb sign' in'the Ydigital Vintev gratorY with 'the wheel-'andfdisc intcgrator, .-the following analogy is profitable. -V t l V The'rate -of occurrence of ones is` analogous to the rate of rotation of a shaft. Ihesign ofthe ones efec-V tively corresponds Vto the direction of .rotation., The Hx',

Vinput has its counterpart VVinY 'the'lead .screwf 17^ drive; and

thro'ugh a resistor IR1', Thisk gate, junction: 36 hastwo other..,c onnections, One oftliesevconnections joinsfjunction 36,di rectly'to the` cathode of.-at:c arry.-.tubefV1 in the, Ygs'tage directly below. Thegcathodeof .carry tube Y-s grounded through aA first diode'gDl.; .The otherfconnectionf joins'gat e junction 36 thrc" 11gh,asecond.diodev Dz'tba common gate output line67.`-,

A VvIn' the normal; operationofthe stage :ofthe X Y the .dz output corresponds to :the Voutpl'lffshfaft,.711Y which l0 the wheel 10 drives. f. A The.Y counter 28 plays the same role astheleadscrew 17,azero value ofthe Y counter corresponds to a centering of the wheel 10 'upon thetdisc 1,3,.whilethetwosgns which `yinay takeindicate the direction .ofsexcursion of 15 the-wheel Y10 from the centerC of Vthedisc 13.

The simplestmathematicalway ofhandling ay function (which increases and decreases; isA to. make the counter add and subtract. If afpositive polarity-pulse 1s madeto indicate a positive Vdy incrementand a negative 20 polarityy pulse Vis made to indicatea. negative y increment,`

they :Yrz counter should add.Y when positive t polarity vpulses are received and subtract whennegative -polaritypulses are received. l

However, positive and'negative values of y, andincreasf .2D

ingvandvdecreasing increments dy offthe variable? are handled in a special manner in thegpresent .embodlment ofthe-invention. VActuallyfthe .digitalintegrator.circuit contains a'Y counter which adds only.V When echange 24-shownineFigure 7,. the,leftftube, 4designated V0, in the s tageis cut bland .thefright tube is., :on ducting=.V Uponthe A,introduction of Ya,negatixffpuls'e frornv the previous stageofftheX counter Zito theggrids of-the1two tubes in thestage shown `in Fgureytheright Vtubein .the stage becomes cut oft andthe vtubeVostaxts to ,conduct The tion/,of current Vthroughthe tuhegyo causes `a 'relatively`r low voltage tobeproducedon the plate ofthertube., yThis Y voltage is introducedthrough the capacitance lCitarid the c resistance YRfyto, the junctionV 3 6,Y and the-. cathode. fof the tube V1 in the stage of the counter 40 showninFigas partof a cathode followercircuit in whichthediodepll serves as ,thegfcathode impedance Becauseaof the .impedance provided bygthe.diodecDbran increase lin v thefurrent through VtheV tube'VI anclthediode D1 produces an increase Vint'voltage,across thediode.Vv Q.; ....nf L Upon the introduction of'a -negativefvoltage to the`r cathode of the tube N1', Ythe voltage between the pla-te and the .cathode of. thetubetyl increases. Y .Whenthe' tube .Y1 v

isconducting, the fin'creasejn voltage. ac1 'oss. theA tube causes: the current thro.ugh the tube and .the .diode D1 to V increase and in .turn Vto.fproduc'elanincrease *.inrvoltag'e ,across theadiode.v YYThe: inc raseinfvoltage .5a ros'sflthe Y diode D1` serves to counteractthe d eclfease"'ri olta'ge". produced ;Qr1`,1the. cathodezotlthe tube. Ybb" the "'satve n-signfrom -{-Y to` YYoccurs inthe dy pulses,the n um4 30. beny in therY- counteryis changed,toitscornplenent The treatment Tof the detailed logic 'of' this operation will beffully Yexplained later, Vbut thefnet'resultfis equivalent',

Y to subtraction in theldigital integratorif af 'cornplemenctary V setof Y gates s used.Y e e Y` 35 iGeneralizingfurther, when theYcounter passes through zero a pulseis transmittedA Vto a ysignindicating hip- Hopi the sign of the dx pulses is remembered by;another tiipV opf The sign of .the'fdzcoutput pulses is controlled *byY VtheV positionsof these two ilipfiop s. .'l3y usingfalcontrol t 4Q circuit, when dx and y haVelikesi'gDS, al;` pulsesare madeY Y positive and whenvdxand y havelunlike sign'sfthe dz pulses aregrnade negativefI'heposition of a third Hip-floplgeeps;KY P4115tfffoftllt` .hlb Vufis' reu1t of u nterb'al-` Ytrackerv the adding, subtraming-complementary.functions7 Y Vane'ztheA Voltage Qu'thefath eiofheub V1 .flills .VAcomplete-lgical-block diagram-oa digital-integratora substantially 'cons tanLMSin' the Ac xtliodeP of 'the tube utilizing the serial :additive transfer-method and employing. Vj islconnected ,t0 the. J'un'tio Q6 Q'he Cathode Qf meansfor handlingthesigns oftheyariables,aappearsfin` the diode D2,the voltage.in theV cathode of t h e ,diode'DgV Y Y Eigureo. Theheavyrsolid lines on thedagramsindicate remains VSubs t;i11 ti: f 1lly constantduringjtbeftirnethat the Vtheniain.Course taken'bytdie-pulses corresponding-tothe c tubeljYl is conducting. yTh1' s-'p'revents anyfpulsejrorn onesjojthe system and thegdashedlines are Vcontrol, 50 appeffllg01.1 the tputline 67. ifi '-'i f", "l voltage'tlines. 1 i ,5: vWhen'the"tube Vli's*not-condueting'the eatljode'fol-` t The X counter is herein designatedi24 and the Y'Vgatce's lower `circuit. f or'med "bythe VtubeY Y1? andthe AYdiodeDl 27,@ asf before. Y The `Y counter which.waspreviously '1 dOeS'nOt Operate to counteract anynegative pulse thatmay -describedfas having twice the number of stages-as theJfX Y Vppal 'at thejunctionlBAs afresult,'then'egat iye pulse i i Y counter 24.is labelledI 4 0. .Theseon-jpopents .haygtht !55 issintroduced tothe eathodeof the diodeDz andis appliedA preferred general arrangement, as'iusrdescribed, for'pro- QSVIL'CUPl-IPUISC O'lrthe linle'l-l l f- Y Y Y:

' vidi'ngserialr transfer of. the y memberfrom c-,tbeY [Qnthebas'isbfthe above,j..an outputpulse appears.on` counterftt). f' i .y 5 t theillle'l'Only'WhSnzitheftube Ydbecomes conductivleat; For this embodimentftheaX'counterfzflxactually has htstme thatthCUlbeYYrSrDQILfCOnductive.; Thisfco'rf' A binary@ stages (the l3th'stage isrshowrrrdashed), which- V 60; responds to a condition where the stages ofY the -fcounterVV 'areY eachewnnecedto; 13. `individual Y gafSL27- The Y 274 'i1-Ud #le Y Coulllfffqshpwnf 'ifligllrfeZimllltanously counterV 40 .has 24 binaryfstagesl;However;fas before- `Stages explained;l not all'of'these Y stagesare connected;tothe.V Y .are prepared` p vide positive'indications o f'puls nth able to pass through the' Vgate's'on acorespondiiigly weightedbasis. For example, -the signalsincthe st 'agefof'V will be explainedlaten. Y the Y counter 28 representing'thebinarydigit YofY rrio'st'V significance are able'to pass through thegates `27'substantially twice as fofterl the ,signals Vin thest'ageofthe -e Y counter' representingVV the binary digitofse; nii tnostl E importantsignificance@ results-"lf th'=. a tl that Ythe "stage in'the Y counter 40.representingtherbinary digitof L most importance is associated with the/stage in the X` Y 'a `usg'clinfthe '75E counter 24 representing thebinry'digit of leastimportance i '.Beforecontinuing the description of thegfune ionsgofr;

y theremaining blocks insFigure 6; theseriahadditiv trans-v '7.01

fefEfwhQd.Will/bemhe;described-2 ff- .in Figure i7 a.fragmentarygdetailedcircuit and every other stage 1n the Y counter is associated with the complementary stage in the X counter. In this way, the signals passing through the Y gates over a period of time corresponding to 2n da' pulses represent the total value of the ydx increments for the period.

The X counter can be considered as a rate division anticoincidence device for the dx pulses. Since the pulses appearing on the common gate output line 67 must al1 be temporally spaced so as to be recognizable as distinct pulses, the binary counter method of distributing the dx pulses ensures that the stages of the Y counter 46 are cycled in time so that no other anti-coincidence devices are needed in the circuit.

The stages in the X counter 24 can be considered in other ways than as rate divisors for the dx pulses. For example, these stages can also be considered as activating means for preparing the various stages in the Y gates 27 on a weighted basis for opening. Because of the operation of the X counter 24 and the Y gates 27 in providing for the passage of the signal indications in the various stages of the Y counter 28 on a Weighted basis, the X counter 24 and the Y gates 27 can be considered as a transfer device when used in combination with the Y counter 28. This transfer device would be equivalent to the transfer device 22 shown in Figure 2 and disclosed above. The transfer device controls the transfer or passage of signal indications from the integrand storage 18 to the remainder accumulator 20 in Figure 2. The Y counter 28 in Figure 4 operates as one type of integrand storage corresponding to the storage 18 in Figure 2 and the R counter 33 in Figure 4 operates as one type of remainder accumulator corresponding to the accumulator 20 in Figure 2.

The serial additive transfer method, used in the embodiment of the digital integrator in Figure 6, can be more clearly described by reference to Figure 8. As in Figure 3, integration is here described as the process of nding the area under a curve y=;f(x). For this specific case, as before, the heights of the rectangular sub-areas An change in fixed increments of the ordinate designated in this case as dye, corresponding to changes of one in the irst stage of the left hand half of Y counter 40 which is the stage numbered as 13th. The widths, on the other hand, of the sub-areas An for this case, vary; these widths being determined by the plurality of discrete incremental changes dx, which occur during a change in y of dye.

In Figure 8, an example is shown where the input rate of dy pulses is greater than the input rate of dx pulses. For approximately two-thirds of the iirst 212 dx pulses, the y ordinate remains xed; then the y ordinate is suddenly considered to increase an amount equivalent to dye. This occurs when a carry pulse is fed from the rst half of the Y counter, i. e., from the 12th stage to the 13th stage. Hence, an effective dy increment dye of the y variable is equivalent to 212 dy pulses. As pulses corresponding to the value of y are conveyed to the dz common output line in accordance with the dx pulses, the sum of the dz output pulses thus obtained corresponds to the value of the area under the curve y=f(x) It is seen by referring to Figure 8 that the integration of the area under the curve f(x) is in error by the crosshatched portion 72 between the curve f(x) and the step curve as obtained by using the y ordinate as generated from the left hand 12 stages of the Y counter 4t2. This error is approximately corrected by use of the 13th stage of the X counter 24 and is known as the trapezoidal correction. Every time 212 dx pulses are received in the X counter a carry pulse is transmitted to its 13th stage. This 13th stage has its non-carry tube connected to the 13th Y gate 27 which is always in an open condition. Thus, every other 212 dx pulse passes through the 13th Y gate and is fed to the output as a dz pulse. This pulse corresponds to an area 212 dy pulses by 212 dx pulses which when divided over two dx transfer cycles adds an area equivalent to the trapezoidal correction shown as the cross-hatched area 73 in Figure 8. This trapezoidal correction is seen to be too large for slopes greater than 45 and too small for slopes smaller than 45. However, on the average, the accuracy this obtained is greater than actually transferring the fuli content of the Y counter during each dx transfer cycle of 224 pulses.

it should be noted that the series additive transfer method of performing integration does not give an incorrect result if the X counter and the Y gates, in the preferred embodiment of the integrating circuit, is made to have the same number of stages as the Y counter. The accuracy, in fact, may be slightly improved if this is done for certain functions, especially those which have a y variable which remains relatively constant. The main consideration for having 13 stages, instead of 24, in the Y counter and the Y gates is to obtain the highest accuracy possible for the least amount of equipment and space.

Referring back to the general block diagram of the digital integrator in Figure 6, the remaining circuits, therein, provide means for handling positive and negative incremental pulses of the variables. The function of these latter circuits will rst be described generally.

As positive and negative polarity pulses are to correspond to positive and negative increment ones of the system, both these polarity pulses are fed into the dx pulse separator 41. In this circuit the negative dx pulses are sent on negative dx line 42 to one grid of a sign dx flipop 44. The positive dx pulses are rst converted to negative polarity pulses and are then sent on positive dx line 43 to the other grid of sign dx flip-op 44. The sign of the dx input pulses is thus recorded and remembered by the state of ip-op 44 at all times. Positive and negative dx control lines 46 and 47, respectively, properly reect the sign of the dx pulses into the dz output pulse former and sign changing circuit 48.

The dx pulse separator 41 sends both polarity dx input pulses into the X counter 24 as negative polarity pulses on the same dx input conductor 49.

As will be disclosed in detail hereafter, the output pulses produced on line 49 are similar to the pulses produced on a line 79 in that all of the pulses representing positive and negative dx increments appear on the line as pulses of negative polarity. In this Way, the dx pulse separator 41 produces only three different types of output signals ,even though four output lines are shown.

A circuit for providing the same functions as the dx pulse separator 41 is shown in Figure 254 of Principles of Television Engineering, by Donald G. Fink (McGraw- Hill Book Company, Inc., first edition, 1940). In Figure 254 of Finks book, signals of positive and negative polarity are introduced to the primary winding of a transformer shown at the left side of the ligure. The signals of positive polarity are separated from the signals of negative polarity by the action of the 6H6 tube and the center tapped secondary Winding of the transformer. The positive signals travel to the top row of circuits in Figure 254 of the Fink textbook and the negative signals travel to the bottom row of circuits in the figure.

The signals introduced to the top row of circuits in the Fink textbook appear as output signals on the plate of the iirst 6F8G tube in the row. Similarly, the signals introduced to the bottom row of circuits in Figures 254 appear as output signals on either the plate of the 1851 tube or the iirst GFSG tube in the row. The output signals from the top row are applied to the grid of the rst 6F8G tube in the middle row and the output signals from the rst GFSG tube in the bottom row are applied to the plate of the rst 6F8G tube in the middle row. The signals on the plate of the rst 6F8G tube in the middle row are introduced to the grid of the second 6F8G tube in the row. The resultant signals on the plate of the second 6F8G tube in the row correspond to the signals produced -on the output lines 49 and 79 of the dx pulse separator 41 shown in Figure 6 of this application.

In a like manner, the positive and negative polarity dy fis input pulses are fed into the dy? pulse separator 51 where the positive pulses 'are converted to negative. pulses both .polarity pulses are then fed into Ythe Y counter 40,01; dy input line 52 as negative pulses. The dy pulse separator 51 can be constructed in a manner similar to Vthe dx,

pulse separator 41 andrin accordance VVwith' the circuits Vfilip-hop, 58 is'rreversed for this case and the complement Vshown in Figure 254 olfV Principles of Television Eng'i-V neering, by Fink. Y A Y Whereas before, the sign of the dr pulses wasdirectly reected in the'state of the associated sign fdr flip-flop 44, in thecase ofthe dy pulses, the positive and negative dy pulses, after appearing as negative polaritypulses on positive and Vnegative dy lines 53 and 54, respectively, pass through an electronic reversing switch 56 and a mechanical reversing Switch 57 before having their sign remem- Y conductor 79 into the dz pulse complementer circuit .78..

bered as one of the states of a circuit called a coniplernent lip-liropV 58. This complement flip-flop SSnhas two input lines designated as a complement grid line 59 and a normal grid line 60. Thus, in accordance with the setting of theelectronic reversing switch 56 and the mechanical reversing switch 57, which determines how positive and negative dy lines S3 and 54 are to be connected to the complementary and normal grid lines 59 and 60, the complementtip-opSS is switched from either state tothe other. The switching of lines 59 and 6i? will be seen` to automatically occur every time the sign of the number y changes. Y ,Y For the purpose of explaining the operation of the Vdigital integrating circuit, themechanical reversing switch 57 will be assumed to be omitted for the present and its function will be explained later.

Each time the complement flip-flop 58 is` switched a complement pulse forming circuit 62 is triggered which feeds a complementing pulse on a common line 63 having parallel connections 64 to each of the stages of the Y counter. VThis complementing pulse changes each of the Y stages toits opposite state, i. e., changes all the ones to zeros and vice versa.

The dy input pulse which results in the complementing pulse'that changes allY the Y stages to its opposite state,

' hasthe additional role of changing the magnitude of y by one Hence, `the dy pulse which caused the complement is delayed in a delay circuit-66 until the transients karising from the change'inlstate of the Y Vcounter have died down. This dy pulse is then added to the complement number now existing in the Y counter which, in eect, changesthe original y by o1-le.

The y number which is serially to be cycled onto the common gate output'line 67 by the dx input'pulses' can thus be seen to be either Ythe-.y numberlor its ones complement. v v Y t AfterY passing through a dz pulse forming circuit 68 in Output line 67, the dz pulses have two possible paths they Vcan take, a normal path 714 or a complementpath 70, before being fed to the dz output pulse former and sign changer circuit 48. .t "Gates 72 and 73,Y inthe complement Vpath 70 and Y normal path 71'respectively, controlled by opposite states ofthe complement ip-op 58, determine which of these paths the dz pulses will follow.

This is'accomplished by gate control lines 75 a nd",74V

which connect the normal dz gate 73 and complement dz gate 72 to the normal and complementtubes Vrespectively of the complement flip-flop 58. l j fY Thus, if the dz pulses from dz pulse former Y68 are Vvolu,me 1, of National lillY Vdue to the transfer of a normal y number, the normal Y' and negative dy Llines'53 and 54 to,` opposite gridlines of Electronics,-'by

dz-gate 72 is now open. The dz complementing Vpulses arenow fedrinto a dz pulse complementer circuit 78 'f located in the complement path 70. Simultaneously, the train of negative polarity dx pulses, which are being fed into the XV counter 24`are fed Von a secondfdx input The function of this circuit, which is Vtobe described in detail later, is -to cancel one-of the dx pulses for each dz complementing pulseV fed therein. Obviously, the dx pulses are'equ'al to Vor of a higherv rate than the dz complementing pulses, thus KVthe' ,dilerence' rate (dhr-dzY comp.) is fed through the open Ycomplement'dz gate 72,V and through the mixer 76 to the dz output pulse former and sign changer circuit 48. Y

When `the number y inthe Y counter 40 vvas'complemented, the dy pulses thereafter. fed .into the Y counter increased the complemented y number. When,Y subsequently, the dz complementing pulses derived by passing thru the y gates with'the Y counter in the complemented conditionV are matched against the stream of dx input pulses, the remaining dx pulses which become the dz output pulses correspond to a pulse stream that would be formed by passing thru the yV gates controlled 'by a normal y number decreased by the number of dy input pulses fed Vinto the Y counter, i. e., the etect of the total operation on the dz output is equivalent to subtracting one pulse from y for each dy pulse as long as the Vcomplementing operation is in effect.

' t It may be noted that the reason the complemented-dz pulses can be matched against theV dx .input .pulses s bef' In Vorder for the Y counter to pass through zero, `the number therein must be decreasingkthus Lthe compleinenting process, equivalent to thersubtracting process, must be active. is characterized by an increaing complement y number in the Y counter. YThis means that when the true y numberV reaches zero,'its complement, held in the counter, will equal the counter capacity..V v

former 82.

The pulse output from zero pulse former 282 triggers ,t

clearly revealed Vby theV detailed descriptionof these circuits, these interconnections 86and 87 prevent thej'occurrence of a zero pulse anda complement pulse at the Wrongtime., 'Y

' The sign y ip-op 84 `is connected byf positive and negative yV 'lines` 88 and 89 respectively to reverse the t electronic reversing switch 56. Every time 'thelsigny ip-flop 84 is triggered, fthe connections from positive 559,60 of theV complement ip-op 58 are in'terchanged.

Positive and negative y control lines 90 and 91, re-

This operation, as has been described,

Thus it is shown that whenever the Y counter reaches Y capacity, it puts out apulse,Y representing a pass through.Y zero for theY y number, `Ywhich triggers zero pulse n 2,841,328 21 22 Spectively, convey the sign of y to the dz output pulse x and y counters. After 21.2 pulses have been applied to former and sign changer circuit 4S which, along with the two counters, they appear like this:

|o |o|o|ololo|o|o|o|ol0|0|1l010|0|0|0|0|0l0|OIOI GIP- dv 24 23 22 21 2O 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 the sign of dx, enables the proper sign of the dz output No output pulses will have been realized. pulses to be determined. After 213-1 pulse inputs, the counters appear so:

122.45678910111213 iz-11111|1|1|1|1|1|111r1|1|el {O=open; C=closed This completes the description of the general block 25 No output pulses have appeared at dz.

diagram of the digital integrator which satises all the The 213 input dx pulse passes through the 13th Y gate requirements previously set forth as desirable. and forms the rst dz output pulse:

12345678910111213 1 -1o|0|o|o|o|o|o|o|o|o1o|o|1| O= ,/{Cld lo1010|o|0l0|o|0i010|0|1|0in1o|0|0|o|olo|o1o|o|0|-dy 2423222120191817161514131211109876543121 Any table of operation of the embodiment illustrated The 3 212th dx input pulse passes through the open in Figure 6 would be arbitrary with respect to the Ydx 12th Y gate to give the second dz output pulse:

and the dy inputs. This is obvious since, for example, a After 214 input pulses have occurred, no additional dz plot of y versus x in Figure 8 is a staircase function appulses appear beyond the Vtwo already eiected:

12345578910111213 L11-lo |olo|o|0|o|010|0|0101o| nl O=open; `/{C=closed IC [CICICICICIOIClClCiOICI Of-)dz proximating a desired curve y=f(x). Therefore, for The next 212 input pulses will eiect one lafz output pulse simplicitys sake, consider the vcondition Where dy=dx. 65 from the 11th stage of the X *counterA through the .open Initial conditions will include zero number content in the Y gate: Y

12.345678910111213 tirfo |0|0lo|01010|0|0l010|1l o;

IO=open; /\O=closed IC lclolcsclclclolcloloml (Mw-da 

